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18-bit, 2 msps pulsar 15 mw adc in lfcsp (qfn) ad7986 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2011 analog devices, inc. all rights reserved. features 18-bit resolution with no missing codes throughput: 2 msps (turbo = hi gh), 1.5 msps (turbo = low) low power dissipation 15 mw at 2 msps, with external reference 26 mw at 2 msps with internal reference inl: 1 lsb typical, 2.5 lsb maximum snr 95.5 db, with on-chip reference 97.0 db, with external reference 4.096 v internal reference: typical drift of 10 ppm/c true differential analog input voltage range: v ref 0 v to v ref with v ref up to 5.0 v allows use of any input range no pipeline delay logic interface: 1.8 v/2.5 v/2.7 v serial interface: spi/qspi?/microwire?/dsp compatible ability to daisy-chain multiple adcs with busy indicator 20-lead 4 mm 4 mm lfcsp (qfn) applications battery-powered equipment data acquisition systems medical instruments seismic data acquisition systems application diagram 2.7nf 15? v? 0v to v ref notes 1. gnd refers to refgnd, agnd, and dgnd. v+ 2.7nf 15? v? v+ in? ad7986 in+ ref avdd, dvdd vio bvdd 5v 2.5v 1.8 v to 2.7v vio sdi sck sdo cnv 3- or 4-wire interface: spi, cs daisy chain (turbo = low) turbo 10f v ref to 0v gnd 1 07956-001 figure 1. general description the ad7986 is an 18-bit, 2 msps successive approximation, analog-to-digital converter (adc). it contains a low power, high speed, 18-bit sampling adc, an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. on the rising edge of cnv, the ad7986 samples the voltage difference between the in+ and in? pins. the voltages on these pins usually swing in opposite phases between 0 v and v ref . it features a very high sampling rate turbo mode (turbo = high) and a reduced power normal mode (turbo = low) for low power applications where the power is scaled with the throughput. in normal mode (turbo = low), the spi-compatible serial interface also features the ability, using the sdi input, to daisy- chain several adcs on a single 3-wire bus and provide an optional busy indicator. it is compatible with 1.8 v, 2.5 v, and 2.7 v using the separate vio supply. the ad7986 is available in a 20-lead lfcsp (qfn) with operation specified from ?40c to +85c. table 1. msop, lfcsp (qfn) 14-/16-/18-bit pulsar? adcs type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 14-bit ad7940 ad7942 1 ad7946 1 16-bit ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941-1 ad7683 ad7687 1 ad7688 1 ad7983 1 ada4841-x ad7684 ad7694 ad7693 1 18-bit ad7691 1 ad7690 1 ad7982 1 ada4941-1 ad7984 1 ada4841-x ad7986 AD8021 1 pin-for-pin compatible.
ad7986 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram ........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit information .................................................................... 13 converter operation .................................................................. 13 conversion modes of operation .............................................. 13 typical connection diagram .................................................... 14 an alog inputs .............................................................................. 15 driver amplifier choice ........................................................... 15 voltage reference input ............................................................ 16 power supply ............................................................................... 16 digital interface .............................................................................. 17 data reading options ............................................................... 18 cs mode, 3 - wire without busy indicator ............................. 19 cs mode, 3 - wire with busy indicator .................................... 20 cs mode, 4 - wire without busy indicator ............................. 21 cs mode, 4 - wire with busy indicator .................................... 22 chain mode without busy indicator ...................................... 23 chain mode with busy indicator ............................................. 24 application hints ........................................................................... 25 layout .......................................................................................... 25 evaluating the ad7986 performance ...................................... 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 3 /1 1 rev. a to rev. b added common - mode input range parameter , table 2 ........... 3 8/10 rev. 0 to rev. a changes to conversion time: cnv rising edge to data avail able (turbo mode/normal mode) parameter, table 4 ....... 5 changes to figure 32 ...................................................................... 22 4/09 revision 0: initial version
ad7986 rev. b | page 3 of 28 specifications av dd = dvdd = 2.5 v, bvdd = 5 v, vio = 1.8 v to 2.7 v, v ref = 4.096 v, t a = ? 40c to +85c, unless otherwise noted. table 2. parameter conditions min typ max unit resolution 18 bits analog input voltage range ( in+ ) ? ( in ?) ?v ref +v ref v absolute input voltage in+, in ? ?0.1 v ref + 0.1 v common - mode input range in+, in ? v ref 0.475 v ref 0.5 v ref 0.525 v analog input cmrr f in = 500 khz 100 db 1 leakage current at 25c acquisition phase 250 na input impedance see the analog inputs section accuracy no missing codes 18 bits differentia l linearity error ?0. 95 0. 60 +1.50 lsb 2 integral linearity error ?2. 50 1.00 +2. 50 lsb 2 transition noise 2.0 lsb 2 gain error, t min to t max 3 ?20 2.4 +20 lsb 2 gain error temperature drift 0. 5 ppm/c zero error, t min to t max 3 ? 0.8 +0.8 mv zero temperature drift 0.3 ppm/c power supply sensitivity a vdd = 2.5 v 5% 4 lsb 2 throughput conversion rate 0 2.00 msps transient response full - scale step 100 ns ac accuracy dynamic range v ref = 4.096 v , internal reference 95.5 9 6.5 db 1 v ref = 5.0 v, external reference 97 98 signal -to - noise ratio , snr f in = 20 khz, v ref = 4.096 v, internal reference 94.5 95.5 db 1 f in = 20 khz, v ref = 5.0 v, external reference 96.5 97.0 db 1 spurious - free dynamic range, sfdr f in = 2 0 khz ?115 db 1 total harmonic distortion 4 , thd f in = 2 0 khz , v ref = 4.096 v, internal r eference ? 11 3 db 1 f in = 20 khz, v ref = 5.0 v, external reference ? 11 4 db 1 signal -to - (noise + distortion), sinad f in = 2 0 khz, v ref = 4.096 v 94.5 9 5.5 db 1 sampling dynamics ?3 db input bandwidth 19 mhz aperture delay 0.7 ns 1 all specifications expressed in decibels are referred to a full - scale input fs r and t ested with an i nput signal at 0.5 db below full scale, unless otherwise specified. 2 lsb means least significant bit. with the 4.096 v input range, one lsb is 31.25 v. 3 see the terminology section. these specifications include full temperature range variation but not the error contribution from the external reference. 4 tested fully in production at f in = 1 khz.
ad7986 rev. b | page 4 of 28 avdd = dvdd = 2.5 v, bvdd = 5 v, vio = 1.8 v to 2.7 v, v ref = 4.096 v , t a = ? 40c to +85c, unless otherwise noted . table 3. parameter conditions min typ max unit internal reference pdref = low output voltage t a = 25c 4.081 4.096 4.111 v temperature drift ?40c to +85c 10 ppm/c line regulation avdd = 2.5 v 5% 50 ppm/v turn -o n settling time c ref = 10 f, c refbufin = 0.1 f 220 ms refin output voltage refin @ 25c 1.2 v refin output resistance 7.5 k? external reference pdref = high , refin = low voltage range 2.4 5.1 v current drain 2 msps, v ref = 5.0 v 500 a refer e nce buffer refin input voltage range 1.2 v refin input current 160 a digital inputs logic levels v il ? 0.3 +0.1 vio v v ih +0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial , 18 bits, twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies a vdd , dvdd 2.375 2.5 2.625 v bvdd 4.75 5. 0 5.25 vio specified performance 1.8 2.5 2.7 v vio range v standby current 1 , 2 a vdd = dvdd = vio = 2.5 v , bvdd = 5.0 v 2.25 a power dissipation with internal reference 2 msps throughput 29 34 mw without internal reference 2 msps throug hput 15 16.5 mw with internal reference 1.5 msps throughput 26 30 mw without internal reference 1.5 msps throughput 11.5 13 mw temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact an analog devices, inc., sales repre sentative for the extended temperature range.
ad7986 rev. b | page 5 of 28 timing specification s avdd = dvdd = 2.5 v, bvdd = 5 v, vio = 1.8 v to 2.7 v, v ref = 4.096 v, t a = ?40c to +85c, unless otherwise noted. 1 table 4. parameter symbol min typ max unit conversion time: cnv rising edge t o data available ( turbo mode/normal mode ) t conv 400/500 ns acquisition time t acq 10 0 ns time between conversions (turbo mode /normal mode ) t cyc 500/660 ns cnv pulse width ( cs mode) t cnvh 10 ns data read during conversion ( turbo mode/normal mode) t data 200/300 ns quiet time during acquisition from last sck falling edge to cnv rising edge t quiet 20 ns sck period ( cs mode) t sck 9 ns sck period (chain mode) t sck 11 ns sck low time t sckl 3 .5 ns sck high time t sckh 3 .5 ns sck falling edge to data remains valid t hsdo 2 ns sck falling edge to data valid delay t dsdo 6 ns cnv or sdi low to sdo d17 msb valid ( cs mode) t en 10 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 8 ns sdi valid setup time from cnv rising edge t ssdicnv 4 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sdi valid hold time from cnv risi ng edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sd i valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 5 ns 1 see figure 2 and figure 3 for load conditions. 500a i ol 500a i oh 1.4v to sdo c l 20pf 07956-002 figure 2 . load circuit for digital interface timing 90% vio 10% vio v ih 1 v il 1 v il 1 v ih 1 t delay t delay 1 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 07956-003 figure 3 . voltage levels for timing
ad7986 rev. b | page 6 of 28 absolute maximum rat ings table 5. parameter rating analog inputs in+, in ? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, bvdd to gnd , refgnd ?0.3 v to +6.0 v a vdd , dvdd , v io to gnd ?0.3 v to +2.7 v a vdd and dvdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 20- lead lfcsp ( qfn) 30.4 c/w lead temperatures vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog inputs section for an explanation of in+ and in ?. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7986 rev. b | page 7 of 28 pin configuration and function descripti ons pin 1 indic at or 1 ref 2 ref 3 refgnd 4 refgnd 5 in? 13 cnv 14 sdi 15 turbo 12 sck 11 dvdd 6 in+ 7 pdref 8vio 10dgnd 9 sdo 18 ag nd 19 bvdd 20 refin 17 agnd 16 a vdd top view (not to scale) ad7986 07956-004 notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. figure 4 . pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 description 1, 2 ref ai reference output/ input voltage. when pdref = low, the internal reference and buffer are enabled , producing 4.096 v on this pin. when pdref = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 v. decoupling is required with or without the internal reference and buffer. this pin is referred to the refgnd pins and should be decoupled closely to the refgnd pins with a 10 f capacitor. 3, 4 refgnd ai reference input analog ground. 5 in ? ai differential negative analog input. 6 in + ai differential positive analog input. 7 pdref di internal reference power - down input. when low, the internal reference is enabled. when high, the internal reference is powered down and an external reference must be used. 8 vio p input/outp ut interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, or 2.7 v). 9 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 10 dgnd p digital power ground. 11 dvdd p digi tal power. nominally at 2.5 v. 12 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 13 cnv di conver t input. this input has multiple functions. on its leading edge, it initiates the conversion s and selects the interface mode of the part: chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode, the data should be read when cnv is high. 14 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 18 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial outpu t signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 15 turbo di conversion mode selection. when turbo = high, the maximum throughput (2 msps) is achieved. the adc does not power down between conversions. when turbo = low, the maximum throughput is lower (1.5 msps). the adc powers down between conversions.
ad7986 rev. b | page 8 of 28 pin no. mnemonic type 1 description 16 avdd p input analog power. nominally at 2.5 v. 17, 18 agnd p analog power ground. 19 bvdd p reference buffer power. nominally 5 .0 v. if an external reference buffer is used to achieve the maximum snr performance with 5 v reference , the reference buffer must be powered down by connecting the refin pin to ground. the external reference buffer must be connected to the bvdd pin. 20 refin ai/o internal reference output/reference buffer input. when pdref = low, the internal band gap reference produces a 1.2 v (typical) voltage on this pin, which needs external decoupling (0.1 f typical). when pdref = high, use an external reference to provide a 1.2 v (typical) to this pin. when pdref = high, and refin = low, the on - chip reference buffer and band gap are powered down. an external reference must be connected to ref and bvdd. 21 (epad) exposed pad ep the exposed pad is not c onnected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 ai = analog input, ai/o = bidirectional analog; di = digital input, do = digital output, and p = power .
ad7986 rev. b | page 9 of 28 typical performance characteristics avdd = dvdd = vio = 2.5 v, bvdd = 5.0 v, v ref = 5.0 v , e xternal r eference ( pdref = h igh, refin = low), unless otherwise noted. 0 65,536 131,072 196,608 262,144 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 code in l (lsb) positive in l = +1.57lsb neg a tiv e in l = ?1.25lsb 07956-005 figure 5 . integral nonlinearity vs. code 0 101 1661 8250 35,204 41,811 34,894 7662 1418 68 3 0 0 5000 10, 000 15,000 20,000 25,000 30,000 35,000 40,000 45,000 3ff6 3ff8 3ffa 3ffc 3ffe 0 counts code in hex 07956-006 figure 6. histogram of dc input at code center (external reference) 0 1 55 547 407 35 0 0 5000 10,000 15,000 20,000 25,000 30,000 35,000 40,000 45,000 3ffec 3ffee 3ff0 3ff2 3ff4 3ff6 3ff8 counts code in hex 3662 12,773 31,020 39,395 29,138 2932 11,107 07956-007 figure 7. histogram of dc input at code center (internal reference) 0 65,536 131,072 196,608 262,144 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 code dn l (lsb) positive dn l = +0.54lsb neg a tive dn l = ?0.60lsb 07956-008 figure 8 . differential nonlinearity vs. code 0 4 142 34 1 0 0 5000 10,000 15,000 20,000 25,000 30,000 35,000 40,000 45,000 3ff5 3ff7 3ff9 3ffb 3ffd 3fff 1 counts code in hex 10,211 38,665 41, 434 30,897 2283 6399 1002 07956-009 figure 9. histogram of dc input at code transition (external reference) 0 1 3 150 1282 6513 6879 1438 165 16 0 0 5000 10,000 15,000 20,000 25,000 30,00 0 35,00 0 40,000 3ffeb 3ffed 3ffef 3ff1 3ff3 3ff5 3ff7 3ff9 co unts co de in hex 18,953 22,077 37,385 36,210 07956-010 figure 10 . histogram of dc input at code transition (internal reference)
ad7986 rev. b | page 10 of 28 0 200k 400k 600k 800k 1m ?180 ?200 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 frequenc y (hz) amplitude (db) 07956-111 f s = 2msps f in = 20khz snr = 97.0db thd = ? 1 14.0db sinad = 97.0db figure 11 . fft plot (external reference) 14 15 16 17 18 80 85 90 95 100 2. 5 3.0 3. 5 4.0 4. 5 5.0 enob ( bits) snr, sinad (db) re fer ence volt age (v) snr sinad en ob 07956-212 figure 12 . snr, sinad, and enob vs. reference voltage 80 85 90 95 10 0 1k 1 0k 100k 1m s in ad (d b) frequ enc y (hz) 07956-013 figure 13 . sinad vs. frequency 0 200k 400k 600k 800k 1m ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 frequenc y (hz) amplitude (db) 07956-114 f s = 2msps f in = 20khz snr = 95.5db thd = ? 1 13.0db sinad = 95.5db figure 14 . fft plot (internal reference) 10 5 11 0 95 100 11 5 12 0 12 5 ?12 0 ?12 5 ?11 5 ?11 0 ?10 5 ?10 0 ?9 5 2. 5 3. 0 3. 5 4.0 4. 5 5.0 sfdr (db) t hd (db) re fer ence volt age (v) thd sfdr 07956-015 figure 15 . thd and sfdr vs. reference voltage ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 1k 10k 100k 1m thd (db) frequency (hz) 07956-216 figure 16 . thd vs. frequency
ad7986 rev. b | page 11 of 28 90 91 92 93 94 95 96 97 98 99 100 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 snr (db referred to full scale) input level (db) 07956-032 figure 17 . snr v s. input level 0 0.5 1.0 1.5 2.0 2.5 3.0 2.375 2.425 2.475 2.525 2.575 2.625 supply current (ma) avdd and dvdd voltage (v) i ref i avdd i dvdd i bvdd i vio 07956-033 figure 18 . operating currents vs. supply voltage 0 0.5 1.0 1.5 2.0 2.5 3.0 ?55 ?35 ?15 5 25 45 65 85 105 125 s upp ly c u rr ent (ma) te mper at ure (c) i ref i avdd i bvdd 07956-034 figure 19 . operating currents v s. temperature 0 2 4 6 8 10 12 14 ?55 ?35 ?15 5 25 45 65 85 105 125 supply current (a) i av dd + i dvdd + i vio temperature (c) 07956-035 figure 20 . power - down currents vs. temperature
ad7986 rev. b | page 12 of 28 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the fi rst code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 22). differenti al nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01) should occur at a level ? lsb above nominal negative full scale ( ?4.095984 v for the 4.096 v range). the last transition (from 011 10 to 011 11) should occur for an analog voltage 1? lsb below the nominal full scale (+4.095953 v for the 5 v range). the gain error is the deviation of the difference between the a ctual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise - free code resolution noise - free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise - free code resolution = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmoni c components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic ran ge is expressed in decibels. it is measured with a signal at ?60 dbf so that it includes all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral com ponents below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - (noise + distortion) (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral compone nts that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied.
ad7986 rev. b | page 13 of 28 th e ory of operation comp control logic switches control busy output code cnv c c 2c 65,536c 4c 131,072c lsb sw+ msb lsb sw? msb c c 2c 65,536c 4c 131,072c in+ ref refgnd in? 07956-011 figure 21 . adc simplified schematic circuit information the ad7986 is a fast, low power, single - supply, precise , 18- bit adc using a successive approximation architecture . the ad7986 features different modes to optimize performance according to the applic ation. in turbo mode, the ad7986 is capable of convert - ing 2,000,000 samples per second (2 msps). the ad7986 provides the user with an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed chann el applications. the ad7986 can be interfaced to any 1.8 v to 2.7 v digital logic family. it is available in a 20- lead lfcsp ( qfn ) that allows space savings and flexible configurations. converter operation the ad7986 is a successive appr oximation adc based on a charge redistribution dac. figure 21 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary - weighted capacitors that are connected to the two comparator inp uts. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to a gnd via sw+ and sw ? . all independent switches are connected to the analog inputs. th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in ? inputs. when the acquisition phase is complete and the cnv input goes high, a c onversion phase is initiated. when the conversion phase begins, sw+ and sw ? are opened first. the two capacitor arrays are then disconnected from the analog inputs and connected to the ref gnd input. therefore, the differential voltage between input in+ and input in ? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between ref gnd and ref, the comparator input varies by binary - weighte d voltage steps (v ref /2, v ref /4 v ref /262 , 144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase , and t he control logic generates the adc output code and a busy signal indicator. because the ad7986 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. conversion modes of operation the ad7986 features two conver sion modes of operation : turbo and normal. turbo conversion mode (turbo = high) allows the fastest conversion rate of up to 2 msps , and does not power down between conversions. the first conversion in t urbo mode should be ignored because it contai ns meanin gless data. for applica tions that require lower power and slightly slower sampling rates, the n ormal mode ( turbo = low) allows a maximum conversion rate of 1. 5 msps , and powers down between conversion. the first conversion in normal mode does contain meaningful data.
ad7986 rev. b | page 14 of 28 transfer functions the ideal transfer characteristic for the ad7986 is shown in figure 22 and table 7 . 100 ... 000 100 ... 001 100 ... 010 01 1 ... 101 01 1 ... 1 10 01 1 ... 11 1 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 07956-012 figure 22 . adc ideal transfer function table 7 . output codes and ideal input voltages description analog input v ref 5 v digital output code ( he ) fsr ? 1 lsb +4.095969 v 0x 1ffff 1 midscale + 1 lsb +3 1.25 v 0x00001 midscale 0 v 0x00000 midscale ? 1 lsb ?3 1.25 v 0x 3ffff ? fsr + 1 lsb ?4.095969 v 0x20001 ? fsr ? 4.096 v 0x20000 2 1 this is also the code for an overranged analog input (v i n+ ? v in ? above v ref ? ref gnd). 2 this is also the code for an underranged analog input (v in+ ? v in ? below ref gnd). typical connection d iagram figure 23 shows an example of the recommended connection diagram for the ad7986 when multiple supplies are available. 2.7nf 15? v? 0v to v ref v+ 2.7nf 15? v? v+ in? ad7986 in+ ref avdd, dvdd dd vio bvdd 5v 2. 5v 1.8v to 2.7v vio sdi sc lk s do cnv tu rb o 10f v ref to 0v gnd 1 07956-016 notes 1. gnd refers to refgnd, agnd, and dgnd. 3- or 4-wire interface: spi, cs daisy chain (turbo = low) figure 23 . typical application diagram with multiple supplies
ad7986 rev. b | page 15 of 28 analog input s figure 24 shows an equivalent circuit of the input st ructure of the ad7986 . the two diodes, d1 and d2, provide esd protection for the analog inputs , in+ and in ?. care must be taken to ensure that the analog input signal does not exceed the reference input voltage (ref) by more than 0.3 v . if the analog input signal exceeds this level, the diodes be come forward - bias ed and start conducting current. thes e diodes can handle a forward - biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the v+ and v ? supplies of the buffer amplifier in figure 23) are different from those of ref , the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short circuit ), the current limitation can be used to protect the part. c pin ref r in c in d1 d2 in+ or in? gnd 07956-014 figure 24 . equiv alent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in ?. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs (in+ or in ?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component composed of serial resistors and the on re sistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, where the switches are close d, the input impedance is limited to c pin . r in and c in make a one -pole, low - pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the ad7986 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to t he input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier cho ice although the ad7986 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7986 . the noise from the driver is filtered by the ad7986 analo g input circuit s one - pole, low - pass filter , made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7986 is 62.5 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 )( 2 .4 43 62.5 log20 n 3db loss ne f snr where: f C 3db is the inpu t bandwidth , in megahertz, of the ad7986 (20 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for examp le, 1 in buffer configuration). e n is the equivalent input noise voltage of the op am p, in nv/ hz. ? for ac applications, the driver should have a thd perfor - mance commensurate with the ad7986 . ? for multichannel multiplexed applications, the driver amplifier and the ad7986 analog input circuit must settle for a full - scale step onto the capaci tor array at a n 18 - bit level (0.0004%, 4 ppm). in the data sheet of the driver amplifier , settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a n 18- bit level and should be verified prior to driver s election. table 8 . recommended driver amplifiers amplifier typical application AD8021 very low noise and high frequency ad8022 low noise and high frequency ada4899 -1 ultralow noise and high frequency ad8014 low power and high frequency
ad7986 rev. b | page 16 of 28 voltage reference in put the ad7 986 allows the choice of a ver y low temperature drift internal voltage reference, an external reference, or an external buffered reference. th e internal reference of the ad7986 provides excellent performance and can be used in almost all applications. internal referenc e, ref = 4.096v ( pdref = low) to use the internal reference, the pdref input must be low. this enables the on - chip band gap reference and buffer, result - ing in a 4.096 v reference on the ref pin (1.2 v on refin) . the internal reference is temperature compensated to 4.096 v 15 mv. the reference is trimmed to provide a typical drift of 10 ppm/c. the output resistance of ref in is 6 k ? when the internal reference is enabled. it is necessary to decouple this pin with a ceramic capacitor of at least 100 n f. the output resistance of refin and the decoupling capacitor form an rc filter , which helps to reduce noise. because the outp ut impedance of ref in is typically 6 k ?, relative humidity (among other industrial contamina nts ) can directly affect the drift characteristics of the reference. a guard ring is typically used to reduce the effects of drift under such circum - stances . howeve r, the fine pitch of the ad798 6 makes this difficult to implement. one solution, in these industrial and other types of applications, is to use a conformal coating, such as dow corning? 1 - 2577 or humiseal? 1b73. external 1.2 v reference and internal buffer (pdref = high) to use an external reference along with the internal buffer, pdref should be high. this powers down the internal reference and allows the 1.2 v reference to be applied to refin, producing 4.096 v (typically) on the ref pin. extern al refere nce (pd ref = high, re f in = low ) to apply an external r eference voltage directly to the ref pin, pdref should be tied high, and re f in should be tied low. bvdd should also be driven to the same potential as ref. for example , if ref = 2.5 v, bvdd should be ti ed to 2.5 v. the advantages of directly using the external voltage reference are: ? the snr and dynamic range improvement (about 1.7 db) resulting from the use of a larger reference voltage (5 v) instead of a typical 4.096 v reference when the internal ref erence is used. this is calculated by ? ? ? ? ? ? = 0.5 096.4 log20 snr ? the power savings when the internal reference is powered down (pdref high). reference decoupling the ad7986 voltage reference input, ref, has a dynamic input impedance that requires careful decou pling be tween the ref and refgnd pins. the layout section d escribes how this can be done. when using an external reference, a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605 ), and a 10 f (x5r, 0805 size) ceramic chip capacitor are appropria te for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference decoupling capacitor with values as sm all as 2.2 f can be used with minimal impact on performance, especially dn l. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and ref gnd pins. power supply the ad7986 uses four power supply pins: a n analog supply (a vdd ) , a buffer supply (bvdd), a digita l supply (dvdd), and a digital input/output interface supply ( vio ) . vio allows direct interface with any logic between 1.8 v and 2.7 v . to reduce the number of supplies needed, vio , dvdd, and a vdd can be tied together. the ad7986 is independent of power s u pply sequencing among all of its supplies. additionally, it is very insensitive to power supply variations over a wide frequency range.
ad7986 rev. b | page 17 of 28 digital interface although the ad7986 has a reduced number of pins, it offers flexibility in its serial interface m odes. when in cs mode, the ad7986 is compatible with spi, microwire?, qspi?, and digital hosts. in this mode, the ad7986 can use either a 3 - wire or a 4 - wire interface. a 3 - wire interface using the cnv, sck, and sdo signals minimizes wirin g connections , which is useful, for instance, in isolated applications. a 4 - wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampli ng or simultaneous sampling applications. when in chain mode, the ad7986 provides a daisy - chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. chain mode is only available in n ormal mode ( turbo = l ow). the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is always selected. in n ormal mode operation, the ad7986 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and tri gger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled i n cs mode if cnv or sdi is low when the adc conversion ends (s ee figure 28 and figure 32) , and turbo must be kept low for both digital interfaces. when cnv is low, readi ng can occur during conversion and acquisition, and when sp lit across acquisition and conversion , as detailed in the following sections. a discontinuous sck is recommended because the part is selected with cnv low, and sck activity begins to clock out data. note that in the following sections, the timing diagram s indicate digital activity (sck, cnv, sdi, and sdo ) during the conversion. however, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading time, t data , because the ad7986 provide s error correc tion circuitry that can correct for an incorrect bit decision during this time. from t data to t conv , there is no error correction , and conversion results may be corrupted. similarly, t quiet , the time from the last falling edge of sck to the rising edge of c n v, must remain free of digital activity. the user should configure the ad7986 and initiate the busy indicator (if desired in normal mode ) prior to t data . it is also possible to corrupt the sample by having sck near the sampling instant. therefore, it is recom - mended to keep the digital pins quiet for approximately 2 0 ns before and 10 ns after the rising edge of cnv, using a disconti nuous sck whenever possible to avoid any potential performance degradation.
ad7986 rev. b | page 18 of 28 d ata reading options there are three different d ata reading options for the ad7986. there is the option to read during conversion, to split the read across acquisition and conversion (see figure 27 and figure 28 ), and in n ormal mode, to read during acquisition. the desired sck frequency largely determine s which reading option to pursue. reading during conversion, fast hosts (turbo or normal mode) when reading during conversion (n), conversion results are for the previous (n ? 1) conversion. reading should only occur up to t data and, because this time is limited, the host must use a fast sck. the required sck frequency is calculated by data sck t edges sck number f __ to determine the sck frequency, follow these examples to read data from conversion (n ? 1). turbo m ode (2 msps ): number_sck_edges = 18; t data = 200 ns f sck = 18/ 200 ns = 90 mhz normal m ode (1.5 msps ): number_sck_edges = 18; t data = 300 ns f sck = 18/ 300 ns = 60 mhz the time between t data and t conv i s an i/o quiet time where digital activity should not occur, or sensitive bit decisions may be corrupt. split- reading , any speed host (turbo or normal mode) to allow for slower sck , there is the option of a split read where data access starts at the current acquisition (n) a nd spans into the conversion (n). conversion results are for the previous (n ? 1) conversion. similar to reading during conversion, split - reading should only occur up to t data . for the maximum throughput, the only time restric tion is that split- reading take place during the t acq (min imum ) + t data ? t quiet time. the time between th e falling edge of sck and cnv rising is an acquisition quiet time, t quiet . to determine how to split the read for a particular sck frequency, follow these examples to read data from conversion (n ? 1) . for t urbo m ode (2 msps ), f sck = 65 mhz; t data = 200 ns number_sck_edges = 65 mhz 200 ns = 13 thirteen bits are read during conversion (n) , and five bits are read during acquisition (n). for n ormal m ode (1.5 msps ), f sck = 50 mhz; t data = 300 ns number_sck_edges = 50 mhz 300 ns = 15 fifteen bits are read during conversion (n) , and three bits are read during acquisition (n). for slow throughputs, the time restriction is dictated by the users required throughput, and the host is free to run at any speed. similar to the reading during acquisition, for slow h osts, the data access must take place during the acquisition phase with additional time into the conversion. note that data access spanning conversion requires the cnv to be driven high to initiate a new conversion, and data access is not allowed when cnv is high. thus, the host must perform two bursts of data access when using this method. reading during acquisition, any speed hosts ( turbo or normal mode ) when reading during acquisition (n), conversion results are for the previous (n ? 1) conversion. maximum th r oughput is achievable in n ormal mode (1.5 msps ); however , in t urbo mode, 2 msps throughput is not achievable. for the maximum throughput, the only time restriction is that the reading takes place during the t acq (min imum ) time. for slow throughputs, the time restriction is dictated by throughput required by the user, and the host is free to run at any speed. thus for slow hosts, data access must take place during the acquisition phase.
ad7986 rev. b | page 19 of 28 cs mode, 3 - wire w ithout busy indicato r this mode is usually used when a single ad7986 is connected to an spi - compatible digital host. the connection diagram is shown in figure 25 , and the corresponding timing is given in figure 26. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7986 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by s ubsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the 18 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. ad7986 sdi sdo cnv sck convert data in clk digital host vio 07956-018 figure 25 . cs mode, 3 - wire without busy indicator connection diagram (sdi high) acquisition (n) acquisition (n + 1) acquisition (n - 1) 1 2 begin data (n ? 1) conversion (n) end data (n ? 1) sck cnv sdo 16 17 conversion (n ? 1) end data (n ? 2) t conv t data 0 (i/o quiet time) (i/o quiet time) 18 16 17 18 1 17 16 15 2 012 sdi = 1 > t conv (quiet time) t cyc t acq t cnvh t quiet t sck t dis t dis t dis t dis t en t en t dsdo t hsdo t data t conv 07956-116 figure 26 . cs mode, 3 - wire without busy indicator serial interface timing (sdi high)
ad7986 rev. b | page 20 of 28 cs mode, 3 - wire with busy indic ator this mode is usually used when a single ad7986 is connected to an spi - compatible digi tal host having an interrupt input. it is only available in n ormal conversion mode ( turbo = low). the connection diagram is shown in figure 27, and the correspond ing timing is given in figure 28 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irr espective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possibl e conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high imped - ance to low impedance. with a pull - up on the sdo line, this transition can be used as an interrupt signal to initiate th e data reading controlled by the digital host. the ad7986 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can b e used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the optional 19 th sck falling edge, sdo returns to high impedance. if multiple ad7986 device s are select ed at the same time, the sdo output pin handles this contention without damage or induced latch - up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. ad7986 sdi sdo cnv sck convert data in clk digital host vio irq vio 47k? turbo 07956-020 figure 27 . cs mode, 3 - wire with busy indicator connection diagram (sdi high) sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition turbo = 0 sdi = 1 t cnvh t acq t quiet (quiet time) 07956-021 figure 28 . cs mode, 3 - wire with busy indicator serial interface timing (sdi high)
ad7986 rev. b | page 21 of 28 cs mode, 4 - wire without busy indicat or this mode is usually used when multiple ad7986 device s are connected to an spi - compatible digital host. a connection diagram example using two ad7986 device s is shown in figure 29 , and the corresponding timing is given in figure 30. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be he ld high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7986 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture t he data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the 18 th sck falling edge , sdo returns to high impedance and another ad7986 can be read. ad7986 sdi sdo cnv sck convert data in clk digital host cs1 cs2 ad7986 sdi sdo cnv sck 07956-022 figure 29 . cs mode, 4 - wire without busy indicator connection diagram acquisition (n) acquisition (n + 1) acquisition (n ? 1) 1 2 begin data (n ? 1) conversion (n) end data (n ? 1) sck cnv sdo 16 17 conversion (n ? 1) end data (n ? 2) 0 t cyc t conv t data t acq t conv t data (i/o quiet time) (i/o quiet time) 18 16 17 18 1 17 16 15 2 012 sdi (quiet time) t hsdicnv t ssdicnv t en t en t hsdo t sck t dis t dis t hsdo t quiet t dsdo 07956-120 figure 30 . cs mode, 4 - wire without busy indicator serial interface timing
ad7986 rev. b | page 22 of 28 cs mode, 4 - wire wit h busy indicator this mode is usually used when a single ad7986 is connected to an spi - compatible digital host with an interrupt input and when it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select th e data reading. this independence is particularly important in applications where low jitter on cnv is desired. this mode is only available in n ormal conversion mode ( turbo = low). the connection diagram is shown in figure 31 , and the correspond ing timing is given in figure 32 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in t his mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but s di must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low imp edance. with a pull - up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7986 then enters the acquisition phase and powers down. the data bits are then clocked out, msb f irst, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. afte r the optional 19 th sck falling edge or sdi going high (whichever occurs first), sdo returns to high impedance. ad7986 sdi sdo cnv sck convert data in clk digital host irq vio 47k? cs1 turbo 07956-024 figure 31 . cs mode, 4 - wire with busy indicator connection diagram (i/o quiet time) sdo d17 d16 d1 d0 t dis t quiet sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv turbo = 0 07956-025 figure 32 . cs mode, 4 - wire with busy indicator serial interface timing
ad7986 rev. b | page 23 of 28 chain mode without b usy indicator this mode can be used to daisy - chain multiple ad7986 device s on a 3 - wire serial interface. it is only available in n ormal c onver - sion mode ( turbo = low). this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shi ft register. a connection diagram example using two ad7986 device s is shown in figure 33 , and the corresponding timing is given in figure 34. when sdi and cnv are low , sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is com plete, the msb is output onto sdo , and the ad7986 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shi ft register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a d igital host using the sck falling edge allows a faster reading rate and consequently more ad7986 device s in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. convert data in clk digital host ad7986 sdi sdo cnv b sck ad7986 sdi sdo cnv a sck turbo turbo 07956-026 figure 33 . chain mode without busy indicator connection diagram sdo a = sdi b d a 17 d a 16 d a 15 sck 1 2 3 39 53 54 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 4 17 t sck t sckh t sckl d a 0 19 38 18 sdo b = sdi c d b 17 d b 16 d b 15 d a 1 d b 1 d b 0 d a 17 d a 16 55 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 17 d c 16 d c 15 d a 1 d a 0 d c 1 d c 0 d a 16 21 35 36 20 37 d b 1 d b 0 d a 17 d b 17 d b 16 t dsdosdi t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi 07956-027 turbo= 0 t ssckcnv figure 34 . chain mode without busy indicator serial interface timing
ad7986 rev. b | page 24 of 28 chain mode with busy indicator this mode can also be used to dai sy- chain multiple ad7986 device s on a 3 - wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applica tions or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7986 device s is shown in figure 35 , and the corresponding timing is given in figure 36. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7986 adc labeled c in figure 35 ) is driven high . this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7986 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb fir st, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n + 1 clocks are required to read back the n adcs. alth ough the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7986 device s in the chain, provided that the digital host has an acceptable hold time. convert data in clk digital host ad7986 sdi sdo cnv c sck ad7986 sdi sdo cnv a sck irq ad7986 sdi sdo cnv b sck turbo turbo turbo 07956-028 figure 35 . chain mode with busy indicator connection diagram sdo a = sdi b d a 17 d a 16 d a 15 sck 1 2 3 39 53 54 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 4 17 t sck t sckh t sckl d a 0 19 38 18 sdo b = sdi c d b 17 d b 16 d b 15 d a 1 d b 1 d b 0 d a 17 d a 16 55 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 17 d c 16 d c 15 d a 1 d a 0 d c 1 d c 0 d a 16 21 35 36 20 37 d b 1 d b 0 d a 17 d b 17 d b 16 t dsdosdi t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi turbo = 0 t quiet 07956-029 figure 36 . chain mode with busy indicator serial interface timing
ad7986 rev. b | page 25 of 28 application hints layout the printed circuit board (pcb) that houses the ad7986 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7986, with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digi tal lines under the device because these couple noise onto the die, unless a ground plane under the ad7986 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it can be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7986 device s. the ad7986 voltage reference input , ref , has a dy namic input impedance and should be decoupled with minimal parasitic induc - tances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and ref gnd pins and connecting them with wide, low impedance t races. finally, the power supplies , vdd and vio of the ad7986 , should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7986 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitc hes on the power supply lines. evaluating the ad798 6 performance the evaluation board package for the ad7986 (eval - ad7986eb) includes a fully assembl ed and tested evaluation board and soft - ware for controlling the board from a pc via the converter evaluat ion and development board, e va l - ced1z .
ad7986 rev. b | page 26 of 28 5 4 paddle 3 1 2 6 bvdd avdd dvdd vio gnd gnd gnd gnd gnd gnd gnd ref ref ref 07956-030 figure 37 . example layout of the ad7986 (top layer) 5v external reference (adr435 or adr445) gnd vio cref bvdd avdd dvdd vio gnd gnd gnd gnd gnd gnd gnd ref ref ref cbvdd cavdd cvio cdvdd 07956-031 figure 38 . example layout of the ad7986 (bottom layer)
ad7986 rev. b | page 27 of 28 outline dimensions 2.65 2.50 sq 2.35 3.75 bsc sq 4.00 bsc sq compliant to jedec standards mo-220-vggd-1 090408-b 1 0.50 bsc pin 1 indic at or 0.50 0.40 0.30 top view 12 max 0.80 max 0.65 ty p sea ting plane pin 1 indic at or coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 39 . 20 - lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp - 20 -4) dimensions shown in millimeters ordering guide model 1 , 2 , 3 temperature range package description packag e option ordering quantity ad7986bcpz ?40c to +85c 20- lead lead frame chip scale package [ lfcsp_vq ] , t ray cp -20 -4 490 ad7986bcpz -rl7 ?40c to +85c 20- lead lead frame chip scale package [lfcsp_vq] , 7 tape and reel cp -20 -4 1,500 eval - ad7986ebz evaluation board eval - ced1z converter eva luation and development board 1 z = rohs compliant part. 2 the eval - ad7986ebz can be used as a standalone evaluation board or in conjunction with the eval - ced1z for evaluation/demonstration purposes. 3 the eval - ced1z allows a pc to control and communicate with all analog devices evaluation boards ending in th e eb designator.
ad7986 rev. b | page 28 of 28 notes ? 2009 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07956 -0- 3/11(b)

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